1. Field of the Invention
The present invention relates to a manufacturing method for a silicon wafer reduced in the penetrating dislocation density by stacking an SiGe layer and a strained Si layer on a silicon substrate.
2. Description of the Background Art
In recent years, a stained silicon wafer obtained by epitaxially growing an SiGe layer on a single crystal silicon substrate and epitaxially growing a strained Si layer on the SiGe layer has been proposed.
In the strained Si layer, a tensile strain is generated due to the SiGe layer having a large lattice constant as compared with Si. This generated strain causes a change in the band structure of Si to release the degeneracy. As a result, the carrier mobility increases.
Accordingly, when this strained Si layer is used as a channel region, a carrier mobility as high as 1.5 times or more that in the case of using a normal bulk silicon can be realized.
For this reason, the strained silicon wafer is attracting attention as a wafer suitable for high-speed MOSFET, MODFET, HEMT and the like.
In order to obtain a good strained Si layer in such a strained silicon wafer, a good SiGe layer, that is, an SiGe layer having a low penetrating dislocation density, a relaxed strain and a smooth surface, must be epitaxially grown as the underlay on a silicon substrate.
However, at the epitaxial growth of an SiGe layer on a silicon substrate, misfit dislocations are generated due to difference in the lattice constant between Si and SiGe, and penetrating dislocations attributable to the misfit dislocations reach the surface at a high density, which brings about a problem that dislocations similarly at a high density are generated also in the strained Si layer formed on the SiGe layer.
Dislocations in the strained Si layer give rise to increase in the junction leak current at the formation of a device element.
Furthermore, there arises a problem that unevenness called cross-hatch is generated on the strained Si layer surface due to penetrating dislocations and residual strain energy. In order to reduce the penetrating dislocation density, various proposals have been heretofore made.
For example, Japanese Patent Examined Publication No. JP-B-2792785 discloses a manufacturing method of a semiconductor device, where an SiGe hierarchy layer of which Ge component is increased at a concentration gradient of about 25%/μm or less is epitaxially grown on a single crystal silicon substrate, an SiGe cap layer of which Ge concentration is constant is then grown, and a strained Si layer is epitaxially grown thereon.
Japanese Patent Unexamined Patent Publication No. JP-A-2002-118254 discloses that in a semiconductor wafer comprising a silicon substrate having thereon a compositionally stepwisely gradient SiGe layer of which Ge compositional ratio gradually increased, an SiGe relaxing layer of which Ge compositional ratio is constant and a strained Si layer. In the semiconductor wafer, the penetrating dislocation density can be reduced by increasing the number of steps.
Japanese Patent Unexamined Patent Publication No. JP-A-2003-197544 discloses a semiconductor substrate wherein the first SiGe layer has a thickness smaller than two times the critical film thickness of causing generation of dislocations due to increase in the film thickness and bringing about lattice relaxation; the second SiGe layer comprises a stepped laminate of multiple layers consisting of an SiGe gradient composition layer of which Ge compositional ratio gradually increasing toward the surface and an SiGe constant composition layer having the same Ge compositional ratio as that on the top surface of the gradient composition layer and being disposed on the gradient composition layer, which are stacked alternately to give a continuous Ge compositional ratio, and the Ge compositional ratio on the bottom surface of the second SiGe layer is lower than the maximum Ge compositional ratio in the first SiGe layer.
As described above, various methods have been proposed with an attempt to reduce the penetrating dislocation density in a strained silicon wafer.
However, in Japanese Patent Examined Publication No. JP-B-2792785, the penetrating dislocation density in Examples is still on the 105 cm−2 order. Such a high penetrating dislocation density may greatly affect the yield in the device process.
Similarly, even in the semiconductor wafer described in Japanese Patent Unexamined Patent Publication No. JP-A-2002-118254, it is difficult to reduce the penetrating dislocation density in the strained Si layer to less than 105 cm−2.
Also, even in the semiconductor substrate described in Japanese Patent Unexamined Patent Publication No. JP-A-2003-197544, when the thickness of the strained Si layer is 20 nm or more, the penetrating dislocation density is not successfully reduced to such an extent as being capable of responding to the level required of the device working region.
Accordingly, in order to realize more speeding up of the operation in MOSFET and the like, a high-quality strained silicon wafer more reduced in the penetrating dislocation density is demanded.